The introduction of Cu metal into multilayer metallization schemes for manufacturing integrated circuits is enabled by the Damascene Cu plating process and is now extensively used by manufacturers of advanced microprocessors and application-specific chips. As the minimum feature dimensions on patterned substrates (wafers) steadily decreases, several consequences of this downward scaling are becoming apparent. One concern is the extendibility of physical vapor deposition (PVD) to produce Cu seed (nucleation) layers for electrochemical plating of the substrate and the features formed on the substrate. These seed layers must become increasingly thinner due to the decreasing minimum feature sizes, and unless significant improvements in the PVD-Cu step coverage are made, it may not be possible to achieve robust continuous film of Cu onto these features (e.g., on the lower sidewall of a via hole) to permit consistent Cu nucleation during Cu electrodeposition.
Alternatives to PVD-Cu seed layers for Cu electroplating include non-Cu seed layers that can be highly conformally deposited by chemical vapor deposition (CVD) or atomic-layer deposition (ALD). One challenge that Cu and non-Cu seeds pose to electrochemical plating processing and the plating equipment is non-uniform thickness of the plated Cu metal onto the seed layer due to the terminal (‘resistive substrate’) effect. The terminal effect is the tendency for the current density to be non-uniform as a result of the ohmic potential drop associated with conducting current from the wafer edge to the entire wafer surface through a thin resistive seed layer. Therefore, new methods are required to improve the thickness uniformity of a Cu metal layer electrochemically plated onto a seed layer.